Название: Digital Logic Design Using Verilog: Coding and RTL Synthesis, 2nd Edition
Автор: Vaibbhav Taraate
Издательство: Springer
Год: 2022
Страниц: 607
Язык: английский
Формат: pdf (true)
Размер: 20.4 MB

This second edition focuses on the thought process of digital design and implementation in the context of VLSI and system design. It covers the Verilog 2001 and Verilog 2005 RTL design styles, constructs and the optimization at the RTL and synthesis level. The book also covers the logic synthesis, low power, multiple clock domain design concepts and design performance improvement techniques. The book includes 250 design examples/illustrations and 100 exercise questions. This volume can be used as a core or supplementary text in undergraduate courses on logic design and as a text for professional and vocational coursework. In addition, it will be a hands-on professional reference and a self-study aid for hobbyists.

The book has 25 chapters and is mainly useful to understand about the RTL design concepts, synthesizable and non-synthesizable Verilog constructs, and basics of testbenches to check for the functional correctness of the design. The book even covers the advanced concepts used in the ASIC design synthesis, with the low power and multiple clock domain design concepts.

Chapter 1 “Introduction” describes about the evolution of logic design, design methodology, and the basics of Verilog. The chapter discusses basics of Verilog Simulation and synthesis flow.
Chapter 2 “Concept of Concurrency and Verilog Operators”, for any language, the operator plays an important role. The Verilog supports various operators, and the chapter discusses the use of these operators in the RTL design.
Chapter 3 “Verilog Constructs and Combinational Design-I” discusses the combinational logic design using the synthesizable Verilog constructs. Also, it discusses the practical and real-life scenarios, useful while implementing combinational designs.
Chapter 4 “Verilog Constructs and Combinational Design-II” discusses RTL design for few of the arithmetic resources and the code converters.
Chapter 5 “Multiplexers as Universal Logic” discusses the efficient RTL coding for multiplexers and parallel versus priority logic.
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Chapter 25 “System-On-Chip (SOC) Design”, the SOC consists of many complex blocks like processors, arbiters, memories, and peripherals. These blocks are discussed in this chapter. This chapter even focuses on the generalized SOC architecture and the SOC design flow.